One type of memory known in the art is Dynamic Random Access Memory (DRAM). One type of DRAM is Single Data Rate (SDR) Synchronous DRAM (SDRAM). In SDR SDRAM, read and write operations are synchronized to a system clock. The system clock is supplied by a host system that includes the SDR SDRAM. Operations are performed on the rising edges of the system clock. SDR SDRAM uses a single data rate architecture. The single data rate architecture has an interface designed to transfer one data word per clock cycle at the data input/output (I/O) pads or pins (DQs). A single read or write access for the SDR SDRAM effectively consists of a single n bit wide, one clock cycle data transfer at the internal memory array and a corresponding n bit wide, one clock cycle data transfer at the DQs.
Another type of DRAM is Double Data Rate (DDR) SDRAM. In DDR SDRAM, the read and write operations are synchronized to a system clock. The system clock is supplied by a host system that includes the DDR SDRAM. Operations are performed on both the rising and falling edges of the system clock. DDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the DQs. A single read or write access for the DDR SDRAM effectively consists of a single 2n bit wide, one clock cycle data transfer at the internal memory array and two corresponding n bit wide, one half clock cycle data transfers at the DQs.
Read and write accesses to SDR SDRAM and DDR SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an activate command, which is followed by a read or write command. The address bits registered coincident with the activate command are used to select the bank and row to be accessed. The address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access.
A Column Address Strobe (CAS) signal is used to latch in the column addresses for selected memory cells and initiate a column access during a read or write operation. The delay between an activate command and the first read command is referred to as the RAS to CAS Delay (tRCD). The delay between CAS pulses during a burst is referred to as the CAS to CAS Delay (tCCD). In both SDR SDRAM and DDR SDRAM, tRCD and tCCD cannot be shorter than minimum times, which are limited by the processing speed of the memory circuit. If tRCD and tCCD are shorter than the minimum times, the memory circuit may fail.
Another type of DRAM is Pseudo-Static Random Access Memory (PSRAM). PSRAM is a low power DRAM having a Static Random Access Memory (SRAM) interface for wireless applications. PSRAMs do not have a separate activate command. The activate command in PSRAMs is automatically executed with a read or write command. Typically, the first access to a memory array of a PSRAM is asynchronous. The read command is typically decoded asynchronously and the initial CAS pulse after the asynchronously decoded read command is issued asynchronously. The subsequent CAS pulses for a burst access after the initial CAS pulse are issued synchronously with the clock. The position of the initial asynchronous CAS pulse can vary with respect to the next, synchronous CAS pulse. The time required to read data out of the memory array is typically longer than a clock period. This delay is referred to as the initial latency, which is the delay between a read command being issued and the first data provided at the DQs.
In PSRAMs, as in SDR SDRAMs and DDR SDRAMs, the tCCD needs to be longer than a minimum time, otherwise the PSRAM may fail. Since the initial CAS pulse is issued asynchronously, the initial CAS pulse and the next, synchronous CAS pulse may move too close together, violating the minimum tCCD requirement, depending on the clock period and the speed of the asynchronous command decode. For typical PSRAMs operating at higher clock speeds, a longer initial latency may be required to maintain the minimum tRCD and tCCD requirements to prevent a memory failure.